1. Field of the Invention
This invention relates to an automatic wiring method for semi-custom semiconductor integrated circuit devices, and more particularly to an automatic wiring method of constructing, on a chip substrate, wiring paths between function blocks which are selected to realize desired LSI circuit function on the chip substrate according to a predetermined routing scheme under the computer-assisted control.
2. Description of the Related Art
Unlike full-custom LSIs (large scale integrated circuits), the semi-custom LSIs have gained in importance for the semiconductor manufactures because they can be developed in a relatively short period of time, and they are superior in flexibility for the use of various LSIs and low in the manufacturing cost. Building block type LSIs and general cell type LSIs are typical examples of semi-custom LSIs wherein selected function blocks (which are also called "modules"), such as a central processing unit (CPU), arithmetic logic unit (ALU), programmable logic array (PLA), random access memory (RAM), read only memory (ROM) or polycell unit, are dispersedly arranged on a semiconductor chip substrate. A properly designed wiring pattern having line segments (called trunks) extending in row and column directions (X and Y directions) is additionally provided in a substrate wiring region formed to surround the function blocks and defined therebetween in order to provide electrical wirings between the function blocks, thus attaining desired LSI functions.
In general, in this type of semi-custom LSI, a computer-aided design method is used to determine the wiring pattern for electrical connection between the function blocks. For example, when a channel wiring method is used for the wiring pattern design, the wiring region on the substrate surface is divided into subwiring regions (known as "channel" to those skilled in the art) so as to correspond to the function blocks arranged on the substrate. Since each of the function blocks is generally formed in a rectangular plane form, each of the sub-wiring regions or channels is formed in a rectangular plane form and arranged adjacent to a corresponding one of the function blocks. Therefore, adjacent channel regions on the substrate are place in contact with each other via a straight-line boundary. The number of wirings or tracks, which extend in the row and column directions and can be formed in each of the channels, is determined based on the surface area of the channel. In order to satisfy the condition of the number of tracks and reduce the length of the wiring to a minimum, the wiring pattern required for attaining desired LSI functions is independently determined for each channel.
For example, the design for the wiring pattern in a corresponding channel between a function block and other associated function blocks is made in a manner that terminals of the function block can be correctly connected to those of the other function blocks. In this case, each connection line is generally formed of lines extending in the row and column directions with the allowable track number taken into consideration. Row and column lines are respectively formed in two conductive layers which are electrically insulatively laminated. Connection at specified portions between the row and column lines is effected via contact holes formed in an insulative layer sandwiched between the two conductive layers. After the wiring pattern has been determined for one channel, the wiring pattern for another channel adjacent thereto is determined by the same process.
However, it is difficult to enhance the integration density of the semi-custom LSI finally obtained according to the conventional automatic wiring design method to a satisfactory degree. This is because dead space for wiring which is not used for the LSI wiring tends to remain in the wiring pattern of the channels finally obtained, making it difficult to effectively minimize the chip size. In particular, the dead space tends to be provided in regions in which the channels are intersected, that is, the long and short sides of the adjacent rectangular channels are in contact with each other. Increase in the dead space undesirably increases the chip size, lowering the LSI integration density.